1. Field of Invention
The present invention relates to a double diffused metal oxide semiconductor (DMOS) device; particularly, it relates to such DMOS device wherein the conduction resistance is reduced.
2. Description of Related Art
FIGS. 1A-1C show a cross-section view, a 3D (3-dimensional) view, and a top view of a prior art double diffused metal oxide semiconductor (DMOS) device 100, respectively. As shown in FIGS. 1A-1C, a P-type substrate 11 has multiple isolation regions 12 by which a device region of the DMOS device 100 is defined. The isolation regions 12 and a field oxide layer 12a for example are a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure, the former being shown in the figures. The DMOS device 100 includes an N-type well 14, a gate 13, a drain 15, a source 16, a body region 17, a body electrode 17a, and the field oxide layer 12a. The well 14, the drain 15 and the source 16 are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The drain 15 and the source 16 are beneath the gate 13 and at different sides thereof respectively. The body region 17 and the body electrode 17a are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. Part of the gate 13 is above the field oxide region 12a in the DMOS device 100. The DMOS device is a high voltage device designed for applications requiring higher operation voltages. However, for operating in the high voltage environment with a higher breakdown voltage, the conduction resistance is usually sacrificed (i.e., higher conduction resistance), and thus the application range of the DMOS device is limited. Particularly, if the DMOS device 100 is an ultra-high voltage device, i.e., with operation voltage higher than 500V, it is a dilemma among the performance of the conduction resistance, the breakdown voltage, and the channel width; increasing the channel width can reduce the conduction resistance, but the manufacturing cost will be increased and the size of the device may be out of a desired range. Therefore, under the limitations of the manufacturing cost, the breakdown voltage and the channel width, it is difficult to further reduce the conduction resistance of the DMOS device.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a DMOS device which reduces the conduction resistance without sacrificing the breakdown voltage, so that the DMOS device may have a broader application range, in which additional manufacturing process steps are not required.